1. Field of the Invention
The present invention relates generally to methods for forming vias through integrated circuit layers within integrated circuits. More particularly, the present invention relates to methods for forming vias through nitrogenated silicon oxide integrated circuit layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device densities have increased and integrated circuit device dimensions have decreased, it has become increasingly important to form through dielectric layers within advanced integrated circuits vias of reduced dimensions in order to provide a means for interconnecting through those dielectric layers patterned conductor layers of similarly reduced dimensions. In order to provide vias of reduced dimensions through dielectric layers within advanced integrated circuits, it is known in the art of advanced integrated circuit fabrication to employ high density plasma reactive ion etch (HDP-RIE) plasma etch methods when formiing those vias, since high density plasma reactive ion etch (HDP-RIE) plasma etch methods typically provide highly anisotropic reactive ion etch (RIE) plasmas through which high aspect ratio straight sided vias of diminished cross-sectional dimensions may be formed through dielectric layers within integrated circuits. When employed within advanced integrated circuits, such high density plasma reactive ion etch (HDP-RIE) plasma etch methods typically employ plasma densities of greater than about 1E11 per cubic centimeter. In comparison, conventional reactive ion etch (RIE) plasma etch methods typically employ plasma densities of less than about 1E9 per cubic centimeter.
When employing high density plasma reactive ion etch (HDP-RIE) plasma etch methods to form vias of diminished dimensions through silicon oxide dielectric layers within advanced integrated circuits, it is common in the art of advanced integrated circuit fabrication to employ a high carbon content fluorocarbon etchant gas, such as hexafluoroethane (C2F6), in order to provide an enhanced silicon oxide dielectric layer to photoresist etch mask layer etch selectivity which is desirable when fabricating within advanced integrated circuits high aspect ratio vias of reduced dimensions through silicon oxide dielectric layers while employing as etch mask layers photoresist layers of diminished thicknesses. While straight sided and flat bottomed vias may be formed through silicon oxide dielectric layers within advanced integrated circuits through high density plasma reactive ion etch (HDP-RIE) methods employing a high carbon content fluorocarbon etchant gas, such as hexafluoroethane (C2F6), problems are nonetheless encountered when attempting to form through such high density plasma reactive ion etch (HDP-RIE) plasma etch methods straight sided and flat bottomed vias through nitrogenated silicon oxide dielectric layers. Nitrogenated silicon oxide dielectric layers formed within advanced integrated circuits may include, but are not limited to, nitrogenated silicon oxide dielectric layers which are formed originally as silicon oxynitride layers, nitrogenated silicon oxide dielectric layers which are formed originally as silicon oxide dielectric layers through chemical vapor deposition (CVD) methods employing nitrogen carrier gas flows and nitrogenated silicon oxide dielectric layers which are formed originally as silicon oxide dielectric layers and subsequently nitrogenated through integrated circuit processes such as but not limited to nitrogen ion implantation processes and nitrogen plasma treatment processes.
A problem typically encountered when attempting to form through a nitrogenated silicon oxide layer within an advanced integrated circuit a via through a high density plasma reactive ion etch (HDP-RIE) plasma etch method while employing a high carbon content fluorocarbon etchant gas, such as hexafluoroethane (C2F6), is that the via so formed is typically formed with straight sidewalls and a rounded bottom rather straight sided sidewalls and a flat bottom. Such straight sided and round bottomed vias formed through nitrogenated silicon oxide dielectric layers within integrated circuits are typically indicative of attenuated etch rates through those nitrogenated silicon oxide dielectric layers, thus providing incompletely etched vias through those nitrogenated silicon oxide dielectric layers.
A pair of structures illustrating this problem is illustrated by reference to FIG. 1a and FIG. 1b. Shown in FIG. 1a is a substrate 10 having formed thereover a pair of patterned silicon oxide dielectric layers 12a and 12b formed through etching a corresponding blanket silicon oxide dielectric layer within a high density plasma reactive ion etch (HDP-RIE) plasma 18 employing a high carbon content fluorocarbon etchant gas, while employing a pair of patterned photoresist layers 16a and 16b as a patterned photoresist etch mask layer. As is illustrated in FIG. 1a, a via 20 defined by the pair of patterned silicon oxide dielectric layer 12a and 12b is formed with strait sidewalls and a flat bottom. In contrast, there is shown in FIG. 1b the substrate 10 having formed thereover a pair of patterned nitrogenated silicon oxide layers 14a and 14b formed through etching within the high density plasma reactive ion etch (HDP-RIE) plasma 18 employing the high carbon content fluorocarbon etchant gas, while similarly employing the pair of patterned photoresist layers 16a and 16b as the patterned photoresist etch mask layer. In contrast with the via 20 defined by the pair of patterned silicon oxide dielectric layers 12a and 12b as illustrated in FIG. 1a, the via 22 defined by the pair of patterned nitrogenated silicon oxide dielectric layers 14a and 14b as illustrated in FIG. 1b is formed with straight sidewalls and a rounded bottom. Vias formed with rounded bottoms through dielectric layers within integrated circuits are undesirable since it is often difficult to subsequently form within those round bottomed vias fully functional or reliable conductor stud layers, such as conductor contact stud layers and conductor interconnection stud layers.
While not being limited to a particular theory as to why vias when attempted to be formed through nitrogenated silicon oxide dielectric layers within advanced integrated circuits through high density plasma reactive ion etch (HDP-RIE) plasma etch methods which employ high carbon content fluorocarbon etchant gases are formed with straight sidewalls and rounded bottoms rather than straight sidewalls and flat bottoms, it is suggested that a nitrogenated carbon compound formed through reaction of: (1) carbon derived from the fluorocarbon etchant gas; with (2) nitrogen derived from the nitrogenated silicon oxide layer, forms a residue layer at the bottom of a via formed through a nitrogenated silicon oxide layer, which residue layer impedes a full anisotropic etching of the via through the nitrogenated silicon oxide layer.
It is thus desirable in the art to provide high density plasma reactive ion etch (HDP-RIE) plasma etch methods employing high carbon content fluorocarbon etchant gas compositions to form through nitrogenated silicon oxide layers within integrated circuits vias with straight sidewalls and flat bottoms. It is towards that goal that the present invention is generally directed.
Various reactive ion etch (RIE) plasma etch methods have been disclosed in the art for etching various layers within integrated circuits. For example, Xiaobing et al., in U.S. Pat. No. 5,387,556, disclose a reactive ion etch (RIE) method for etching aluminum containing layers within integrated circuits. The method employs a hydrogen chloride-chlorine-nitrogen etchant gas composition which provides a substantially anisotropic and particulate contaminant free aluminum containing layer reactive ion etch (RIE) method in comparison with otherwise conventional aluminum containing layer reactive ion etch (RIE) methods which employ a boron trichloride-chlorine-nitrogen etchant gas composition.
In addition, Yanagida, in U.S. Pat. No. 5,338,399, discloses a reactive ion etch (RIE) method for etching within integrated circuits various silicon containing dielectric layers with high etch rate, high etch selectivity and low particulate contamination. The method employs an etchant gas composition comprising a cyclic saturated fluorocarbon compound or a cyclic unsaturated fluorocarbon compound, along with a substrate temperature of less than 50 degrees centigrade.
Finally, Namose, in U.S. Pat. No. 5,294,294, discloses a reactive ion etch (RIE) method for etching with low selectivity, improved manufacturability and improved properties within integrated circuits silicon oxide layers formed with diverse properties. The method employs an etchant gas composition comprising a saturated non-cyclic fluorocarbon gas and an inert gas. The inert gas provides an adsorption layer at the etching surface of the silicon oxide layer(s) to be etched, which adsorption layer buffers fluorine radicals formed from reactive ion etch (RIE) plasma activation of the saturated non-cyclic fluorocarbon gas.
Desirable in the art are additional reactive ion etch (RIE) plasma etch methods through which vias may be formed with straight sidewalls and flat bottoms through nitrogenated silicon oxide layers within advanced integrated circuits. More particularly desirable in the art are additional high density plasma reactive ion etch (HDP-RIE) plasma etch methods through which vias, including but not limited to contact vias and interconnection vias, having straight sidewalls and flat bottoms may be formed through nitrogenated silicon oxide layers within advanced integrated circuits. It is towards the foregoing goals that the present invention is more specifically directed.